1. Technical Field
The present invention relates to a test apparatus. More particularly, the present invention relates to a test apparatus that tests a device under test by using a plurality of test control programs.
2. Related Art
As a test apparatus that tests a device under test such as a semiconductor circuit, a test apparatus that uses a plurality of testing units is known. For example, the plurality of testing units are disposed to correspond to a plurality of devices under test or to a plurality of pins of a device under test. Each testing unit tests a corresponding device under test by sending signals to and receiving signals from the device under test.
The test apparatus stores in advance a plurality of test control programs corresponding to the plurality of testing units. The test apparatus controls each testing unit by executing each test control program.
Furthermore, the plurality of testing units are connected to a single control bus and are mapped in the control bus address space. More specifically, an address in the control bus address space is allocated for each testing unit.
Here, causing a control processor of the test apparatus to control each testing unit by mapping each control bus address space to an address space of the control processor is considered. However, there are cases where the control bus address space cannot be mapped to the control processor address space because, for example, the control bus address space is too large for the control processor address space.
In such a case, providing a single address register that designates an address in the control bus and a single data register used for transmitting and receiving data to and from a testing unit corresponding to the designated address is considered. In this case, the control processor generates address data that designates a testing unit corresponding to each test control program and test data that controls the testing units by executing each test control program and writes the generated data onto the address register and the data register.
The data register controls the testing unit designated by the address data written onto the address register based on the test data written onto the data register itself By doing this, the plurality of testing units can be controlled to test the devices under test, even when the control bus address space cannot be mapped onto the control processor address space.
When using just one grouping of the address register and the data register, however, exclusion control or the like must be implemented, resulting in cases where each testing unit cannot operate correctly. For example, while a test control program A is being executed in the control processor, there are cases where the testing unit cannot be controlled correctly because of an interruption or the like when a task switch to a test control program B occurs.
As a more specific example, a case will be explained in which test control program B is executed to perform access D2 for an address A2 of the control bus after test control program A is executed to perform access D1 for an address A1 of the control bus. First, the control processor writes the address A1 to the address register. It is assumed that the task switch to the test control program B occurs here.
In such a case, the control processor executes the test control program B to perform access D2 for the address A2 by writing the address A2 to the address register and writing the access D2 to the data register. It is assumed that a task switch back to the test control program A occurs here.
The control processor again executes the test control program A to write the access D1 onto the data register. However, because the address A2 is written to the address register, the access D1 that should be performed for the address A1 is instead performed for the address A2. In this manner, a problem arises that the expected operation cannot be performed when a task switch arises for some reason in a case where one grouping of the address register and the data register is used.
In response to this problem, performing control such as the exclusion control, a thread control, or interrupt disabling is considered. However, the test control program or the like must be programmed for such control, which increases the chances of a bug arising in the programming and also increases the time necessary to perform the program.